1. Field of the Invention
The present invention generally relates to multi-layer wiring substrates which are used in, for example, Multi-Chip Modules (MCMs), and more particularly to a multi-layer wiring substrate having a multi-film wiring portion which is formed by stacking a plurality of films flatted accurately by means of a Chemical Mechanical Polishing (CMP) method.
2. Description of the Related Art
In recent years, with the increase of high density and the number of leads of Large Scale Integrated (LSI) semiconductor dice, substrates for interconnecting these dice need to be manufactured with high density as well.
In order to manufacture a multi-layer wiring substrate that can support the above-mentioned situation, there is a well-known method where the multi-layer wiring substrate is manufactured by mounting a multi-film wiring portion on a main substrate thereof.
Conventionally, in a case of forming the multi-film wiring portion, there is a strong possibility that a step may be formed between a wiring region where wires are laid and an unwiring region where wires are not laid. Since the step may cause the breaking of the wires laid therein, it should be eliminated so that each of the films can be flatted accurately.
Further, the CMP is well known as a method of flatting the films accurately, where only convex portions on the films are selected and then polished by a polishing pad while polishing liquid containing silica particles is introduced.
FIG. 1 is a cross-sectional diagram for illustrating a conventional process using the CMP for manufacturing a multi-layer wiring substrate. In this diagram, 1a through 1g denote stacked films, 2a through 2d denote wires, 3 denotes a wiring region where the wires 2a through 2d are laid, 4 denotes a soft peripheral portion which surrounds the wiring region 3 and where no wires are laid, 5 denotes a main substrate on which the stacked films 1a through 1g are mounted, and 6 denotes a multi-film wiring portion 6 which is formed by the stacked films la through 1g. 
As shown in FIG. 1, however, when the films 1a through 1g are each accurately polished by means of the CMP, the soft polishing pad is deformed and stuck to an insulating film of the soft peripheral portion 4. Thereby, the peripheral portion 4 is thus deeply polished and a step between the peripheral portion 4 and the wiring region 3 is generated on each of the films 1a through 1g. If the films 1a through 1g are stacked as they are to form the multi-film wiring portion 6, then the peripheral portions 4 thereof are deformed and hung down, and the wires 2a through 2d laid therein may contact each other (see a state shown by xe2x80x9caxe2x80x9d in FIG. 1).
The contacting of the wires is highly undesirable because shoring may occur as a result of mounting the thus-configured multi-film wiring portion on the main substrate 5 to form a multi-layer wiring substrate.
Furthermore, since the peripheral regions 4 of the stacked films 1a through 1g are thus polished and deformed, outside moisture cannot be effectively protected for invading the wiring regions 3 of the stacked films 1a through 1g. As a result, characteristics of the multi-layer wiring substrate are degraded.
It is a general object of the present invention to provide a multi-layer wiring substrate, in which the above disadvantages can be overcome.
Another and a more specific object of the present invention is to provide a multi-layer wiring substrate having a plurality of stacked films which are flatted accurately by means of a Chemical Mechanical Polishing (CMP) method.
The above objects and other objects of the present invention are achieved by a multi-layer wiring substrate comprising:
a main substrate; and
a plurality of insulating films stacked on said main substrate,
said insulating films having wiring patterns formed on wiring regions thereof and dummy wiring patterns formed on peripheral regions of said wiring regions.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.